1. Field of the Invention
The present invention relates to a test apparatus.
2. Description of the Related Art
As high-speed data transmission methods for data transmission between semiconductor devices, a source synchronous method, a forwarded clock method, a CDR (Clock Data Recovery) method, etc., are known.
With the source synchronous method, in addition to a data signal, a clock signal is transmitted via two transmission lines in synchronization with the data signal. For example, where the transmission rate is 1.6 GHz, an 800 Mhz reference clock and 1.6 Gbps of data, severally assigned to the positive edge and the negative edge of the reference clock, are transmitted. On the receiver side, the data is latched at a a positive edge timing or a negative edge timing of the reference clock. That is to say, the data and the clock signal output from the transmission device correspond to one another in a one-to-one manner.
In contrast, with the forwarded clock method, the data transmission frequency is an integral multiple of (n times) the reference clock frequency. The device on the receiver side multiplies the reference clock by n by means of a PLL circuit, and latches the data using the clock thus multiplied. On the other hand, with the CDR method, 8 B/10 B encoding is subjected to a serial data sequence so as to embed the clock signal in the serial data sequence. The receiver device extracts the clock signal from the serial data sequence, reproduces the clock signal thus extracted, and latches each data item contained in the serial data sequence.